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U9280M-H
Microcontroller with Transponder Interface
The U9280M-H IC is a multi-chip module for remote control and contactless ID systems. It consists of the M44C092 microcontroller and U3280M transponder interface circuit with EEPROM. A coil connected to the transponder interface serves as wireless bidirectional communication interface as well as power supply for the C and the interface. As transponder, the device is supplied by a magnetic RF field applied at the coil. For IRor RF-transmitter applications, it can be supplied by a battery. The C supports with its built-in timers a wide range of IR- and RF-transmission modes such as burst-modulation modes, PWM-, NRZ-, Manchester- and Biphase coding.
Features
D D D D D D D D D D D D D 4-bit HARVARD architecture 4K 8-bit application ROM 256 4-bit RAM 32 16-bit EEPROM 10 bidirectional I/Os 4 external interrupt inputs (SSO20) 8 interrupt levels 2 8-bit multifunction timer/counter Interval timer with watchdog Two-wire serial interface Voltage supervisor On-chip RC oscillator On-chip crystal oscillator
Benefits
D Contactless power supply and communication interface D Power management for contactless- and batterypower supply D Shift-register-supported modulator and demodulator stages D Low power consumption D Active mode < 300 A @ 2 V and 1 MHz system clock frequency (2 s instruction cycle) D Power-down mode < 1 A D Supply voltage 2.0 V to 6.5 V D High-level language programming in qFORTH D Operating speed: 1 - 10 s instruction cycle (2 s @ VDD = 2 V)
C
VBatt VDD OSC2 OSC1/Rosc
U9280M-H transponder interface
Damping stage Field/GAP detect Coil 1 Rectifier 512-bit EEPROM memory Serial interface Biphase modulator
VSS FC MOD NGAP
M4xC092 microcontroller
Reset voltage monitor Oscillators clock management
BP50/INT6
Power management
ROM RAM 4-bit CPU core
MCL
Timer/ counter
BP53/INT1 BP23 BP20/NTE
Coil 2 Clock extractor
w1
Serial interface
Modulator/ demodulator I/O-Ports
BP60/T3O BP63/T3I
BP40/ SC/INT3
BP43/ SD/INT3
BP42/ T2O
BP41/ VMI/ T2I
14002
Figure 1. Block diagram
Rev.A1, 09-Nov-99
1 (20)
Preliminary Information
U9280M-H
COIL 1 COIL 2 VBatt VDD BP40/SC/INT3 BP53/INT1 BP50/INT6 OSC1 OSC2 BP60/T3O
1 2 3 4 5 6 7 8 9 10 Figure 2. Pinning SSO20 Table 1. Pin Description (SSO20 Package) 20 19 18 17
NGAP MOD FC VSS BP43/SD/INT3 BP42/T2O BP41/VMI BP23 BP20/NTE BP63/T3I/INT5
U9280M-H
16 15 14 13 12 11
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VSS UBatt VDD Coil1 Coil2 NGAP MOD FC BP60/T3O BP63/T3I/INT5 BP50/INT6 BP53/INT3 BP40/SC/INT3 BP41/VMI BP42/T2O BP43/SD/INT3 BP20/NTE BP23 OSC1/Rosc OSC2 Circuit ground Power-supply voltage input to connect a battery Power-supply voltage for the C and EEPROM. At this pin a capacitor (0.5 to 10F) must be connected to buffer the voltage during field supply and to block the VDD of the C. 1 Coil input 1. Pin to connect a LC antenna for communication and field supply 2 Coil input 2 see above 20 Gap detect output - front end. Must be connected to the demodulator input Pin T3I. 19 Modulation input - front end. Must be connected to the modulator output Pin T2O. 18 Field clock output of the clock extractor 10 Bidirectional I/O-line / Timer 3 output/ modulator output 11 I/O-port line / INT5 interrupt input / Timer 3 input / demodulator input 7 I/O-port line / INT6 interrupt input (falling or rising edge sensitive) 6 I/O-port line / INT3 interrupt input (falling or rising edge sensitive) 5 I/O-port line / serial clock line / INT3 input (falling edge sensitive) 14AAAAAAAAAAAAAAAAAAAAAAAAA I/O-port line / Voltage monitor input / Timer 2 input 15 I/O-port line / Timer 2 output / modulator output 16 I/O-port line / serial data line / INT3 input (falling edge sensitive) 12 BP20-I/O-port line / test mode input. This input is used to control the test modes. During POR it must not be connected with a low impedance to VDD. 13 I/O-port line 8 Oscillator- or external system-clock input / input for RC-oscillator resistor 9 Oscillator output 2 (20) Rev.A1, 09-Nov-99
Name
Pin 17 3 4
Function / Alternate Function
Preliminary Information
U9280M-H
Table of Contents
1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 M44C092 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 The U3280M Transponder Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Field Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Gap Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Wake-up Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 U3280M Signals and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.1 Automatical Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.2 Controlling the Power Management via the Serial Interface . . . . . . . . . . . . . . . . . 1.8.3 Buffer Capacitor CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9.1 Serial Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.1 EEPROM - Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.2 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.3 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.4 Initialization after a Reset Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.5 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Common Features U9280M-H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Common DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 DC Characteristics - Microcontroller M44C092 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 DC Characteristics - Transponder Interface U3280M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 AC Characteristics - Transponder Interface U3280M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Order Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 5 5 5 5 5 6 6 6 7 7 7 7 8 8 8 9 10 10 11 12 12 12 12 13 13 14 16 17 18 18 18
2
3 4
Rev.A1, 09-Nov-99
3 (20)
Preliminary Information
U9280M-H
1 Functional Description
1.1 M44C092
The U9280M-H multi-chip module contains a microcontroller and a transponder IC mounted in a single package. Everything necessary for remote control and wireless identifcation systems is integrated: inputs to connect keys, outputs to control an IR- or RF transmitter and to drive indicator LEDs, an EEPROM to store key code and identifiers, and an interface for contactless communication and power supply. The U3280M is a transponder interface consisting of an analog front end for contactless data communication and power supply, and a serial 512-bit EEPROM. In addition, it includes power management to switch the battery or magnetic-field power supply. For modulation and demodulation of the magnetic field, the device has input and output pins to connect the microcontroller. The MOD, NGAP and FC Pins can be connected externally to the modulator, demodulator and timer I/O pins of the microcontroller. Access to the EEPROM is possible via a two-wire serial interface. The M44C092 microcontrollers are equipped with compatible two-wire serial interface to communicate with the U3280M. In the U9280M-H the serial interfaces of the transponder interface and the microcontroller are linked internally.
V SS VDD
The M44C092 microcontroller is a member of the TEMIC 4-bit single-chip microcontroller family . It is especially designed for remoted-control applications. It consists of an advanced stack-based 4-bit CPU core with 4 K ROM, 256 nibble of RAM and on-chip peripherals. The CPU is based on the HARVARD architecture and contains an interrupt controller with 8 prioritized interrupt levels. The peripherals include parallel I/O ports, two 8-bit programmable multifunction timer/counters, a two-wire serial interface, an interval timer with watchdog function and a voltage supervisor. The serial interface supports, together with the timers, a modulator and demodulator stage for Manchester, Biphase and pulse-width modulation and demodulation. The integrated clock generator contains a RC-, a 32-kHz crystal, a 4-MHz crystal oscillator and a programmable input to use an external clock. Note: In the U9280M-H not all I/O pins of the M44C092 are available (see 'Pin Description'). The microcontroller is fully described in the MARC4 M44C092 data sheet.
OSC1 OSC2
Brown-out protect. RESET Voltage monitor External input VMI BP10 Port 1 BP13 BP20/NTE Data direction Port 2 BP21 BP22 BP23
External RC Crystal oscillators oscillators clock input Clock management
UTCM Timer 1 interval- and watchdog timer Timer 2 8/12-bit timer with modulator SSI Serial interface Timer 3 8-bit timer / counter with modulator and demodulator
T2I T2O SD SC T3O T3I
ROM
4 K x 8 bit
RAM
256 x 4 bit
MARC4
4-bit CPU core I/O bus
Data direction + interrupt control Port 5
Data direction + alternate function Port 4
Data dir. + alt. function Port 6
BP50 BP52 BP42 BP40 INT1 INT3 T2O BP43 INT6 BP53 BP51 SC BP41 INT3 VMI INT1 INT6 SD T2I
BP60 T3O
BP63 T3I
13361
Figure 3. Block diagram M44C092
4 (20)
Rev.A1, 09-Nov-99
Preliminary Information
U9280M-H
1.2 The U3280M Transponder Interface
The transponder interface contains a rectifier stage to rectify the AC from the coil inputs and to supply itself and an additional microcontroller device with power from a LC-resonant circuit at the coil inputs. It is also possible to supply the device via the VBatt-input with DC from a battery. The built-in power management switches automatically between battery supply (VBatt pin) and coil supply. It switches to coil supply if a field is applied at the coil and switches back to battery if the field is removed. The voltage from the coil or the VBatt pin is output at the VDD pin to supply the microcontroller device. At the VDD pin a capacitor must be connected to smooth and buffer the supply voltage for the transponder interface and the microcontroller. This capacitor is also used to buffer the supply voltage during communication (damping and gaps in the field). For communication, a damping-stage and a gap-detect circuitry is on the chip. By means of the damping stage the coil voltage can be modulated to transmit data via the field. It can be controlled with the modulator input (MOD pin) via the microcontroller. The gap detection circuitry detects gaps in the field and output the gap/field signal at the gap detect output (NGAP pin). It can be used to receive data via a modulated field and to check if a field is applied at the coil. For the storage of data such as key codes, identifiers and configuration bits, a 512-bit EEPROM is available on the chip. It can be read and written by the microcontroller via an I2C-compatible two-wire serial interface.The serial interface, the EEPROM and the microcontroller are supplied with the voltage at the VDD pin. That means the microcontroller can read and write the EEPROM if the supply voltage is in the operating range. The U3280M contains additional operating modes to support a wide range of applications. These modes can be controlled via the serial interface. The power management can be switched off by software to disable the automatic switching between battery and field. This supports applications with battery supply only. There is an on-chip Biphase and Manchester modulator. It can be selected and controlled via the serial interface with a special mode control byte. If this modulator is used the external connection to the modulator input is not necessary. modulator can be controlled via the MOD pin. A high level "1" increases the current into the coil inputs and damps the coil voltage. A low level "0" decreases the current and increases the coil voltage. The modulator generates a voltage stroke of about 2 Vpp at the coil. A high level at the MOD input makes the maximum of the field energy available at VDD. During a reset a high level at the MOD input causes the optimum conditions for starting the device and charging the capacitor at VDD after the field is applied at the coil. Digital Input to Control the Damping Stage (MOD) MOD=0: coil undamped V COIL_peak + VDD 2 ) V CMS + V CU MOD=1: coil damped V COIL_peak + VDD 2 + VCD
VCMS = VCID: modulation voltage stroke @ coil inputs Note: If the automatically power management is disabled the internal front end VDD is limited at VDDC. In this case the value VDDC must be used in the formula above.
1.4
Field Clock
The field clock extractor of the interface makes the field clock available for the microcontroller. It can be used to supply timer inputs to synchronize modulation and demodulation with the field clock.
1.5
Gap Detect
The transponder interface can also receive data. The base station modulates the data with short gaps in the field. The gap-detection circuit detects these gaps in the magnetic field and outputs the gap/field signal at the NGAP pin. A high level indicates that a field is applied at the coil and a low level indicates a gap or that the field is off. The microcontroller must demodulate the incoming data stream at one of its inputs. Digital Output of the Gap Detection Stage (NGAP) NGAP=0: gap detected / no field V COIL_peak + VFDOFF NGAP=1: field detected V COIL_peak + VFDON Note: No amplifier is used in the gap detection stage. A digital Schmitt trigger evaluates the rectified and smoothed coil voltage.
1.3
Modulation
1.6
Wake-up Signal
The transponder interface can modulate the magnetic field by a modulator to transmit data to a base station. It modulates the coil voltage by varying the coil`s load. The Rev.A1, 09-Nov-99
If a field is applied at the coil of the transponder interface the microcontroller can be woken up with the wake signal at the NGAP pin. For that purpose the NGAP pin must be 5 (20)
Preliminary Information
U9280M-H
connected to an interrupt input of the microcontroller. A high level at the NGAP output indicates an applied field and can be used as wake signal for the microcontroller via an interrupt. If no battery voltage is available at VBatt the controller starts with a power-on-reset after the voltage of the buffer capacitor at VDD is loaded by the field above the power-on-reset level. The wake signal is generated if the power management switches to field supply. The field detection stage of the power management has low-pass characteristics to avoid the generation of wake signals and unnecessary switching between battery and field supply in case of interferences at the coil inputs.
1.7
U3280M Signals and Timing
MOD
VCU VCMS Coil inputs
14101
VCD
Figure 4. Modulation
tFGAP1 VFDON
Coil inputs
tFGAP0
VFDOFF
1. edge used as wakeup signal
NGAP Field clock FC
Battery supply Battery supply
Power management
tBFS
Coil supply if automatically power management is enabled
tFBS
Figure 5. Gap detection and battery to field switching
1.8
Power Supply
the field is modulated by gaps and damping. The EEPROM and the microcontroller always operate with the voltage at the VDD pin.
The U3280 has a power management that handles two power-supply sources. Normally, the IC is supplied by a battery at the VBatt pin. If a magnetic field is applied at the LC-resonant circuit of the device the field detection circuit switches from VBatt to field supply. During field supply the VDD voltage is limitted at 3 V. The VDD pin is used to connect a capacitor to smooth the voltage from the rectifier and to buffer the power when
1.8.1
Automatical Power Management
There are different conditions to switch from the battery to field and vice versa.
6 (20)
Rev.A1, 09-Nov-99
Preliminary Information
U9280M-H
VCoiluVFDON for tutBFS voltage is in the range of 100 - 300 mV. During gaps and damping the capacitor is used to supply the device, that means the size of the capacitor depends on the length of the gaps and damping cycles. Field supply Example: For a supply current 350 A, 200 mV ripple @ VDD
Battery supply (VBatt)
VCoiltVFDOFF for tutFBS
Figure 6. Switch conditions for the power management
The power management switches automatically from battery to field if the rectified voltage (Vcoil) from the coil inputs becomes higher than field-on-detection voltage (VFDON) even if no battery voltage is available (0 < VBatt < 1.8 V). It switches back to battery if the coil voltage becomes lower than the field-off-detection voltage (VFDOFF). The field-detection stage of the power management has low-pass characteristics to suppress noise. An applied field needs a time delay tBFS (battery-to-field switch delay) to change the power supply. If the field is removed from the coil the power management will generate a reset for the microcontroller.
1.8.2
Controlling the Power Management via the Serial Interface
The automatic mode of the power management can be switched off and on by a command from the microcontroller. If the automatic mode is switched off the IC is always supplied by the battery up to the next power-on reset or to a switch-on command. The power management-on and -off command must be transferred via the serial interface. If the power management is switched off and the device is supplied from the battery it can communicate via the field without load the field. This mode can be used to realize applications with battery supply if the available field is too weak to supply the IC with power.
1.8.3
Buffer Capacitor CB
The buffer capacitor connected at VDD is used to buffer the supply voltage for the microcontroller and the EEPROM during field supply. It smooths the rectified AC from the coil and buffers the supply voltage during modulation and gaps in the field. The size of this capacitor depends on the application. It must be of a dimension so that during modulation and gaps the ripple on the supply
Rev.A1, 09-Nov-99
Preliminary Information
AAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAAAA
1.9 Serial Interface
The transponder interface has an I2C-like serial interface to the microcontroller for read and write accesses to the EEPROM. In a special mode the serial interface can also be used to control the Biphase/Manchester modulator or the power management of the U3280M. The serial interface of the U3280M device must be controlled by a master device (normally the M4xC09x microcontroller) which generates the serial clock and controls the access via the SCL- and SDA-line. SCL is used to clock the data in and out of the device. SDA is a bidirectional line used to transfer data into and out of the device. The following protocoll is used for the data transfers.
No Field Supply During 250 s 500 s
Necessary CB 470 nF 1000 nF
1.9.1
Serial Protocol
D Data states on the SDA line changing only while SCL is low. D Changes in the SDA line while SCL is high will be interpreted as START or STOP condition. D A START condition is defined as high-to-low transition on the SDA-line while the SCL-line is high. D A STOP condition is defined as low-to-high transition on the SDA-line while the SCL-line is high. D Each data transfer must be initialized with a START condition and terminated with a STOP condition. The START condition wakes the device from standby mode and the STOP condition returns the device to stand-by mode. D A receiving device generates an acknowledge (A) after the reception of each byte. For that the master device must generate an extra clock pulse. If the reception was successful the receiving master or slave device pulls down the SDA-line during that clock cycle. If in transmit mode an acknowledge is not detected (N) by the interface, it will terminate further data transmissions and will go into receive mode. A master device must finish its read operation by a not acknowledge and then issue a stop condition to place the device into a known state.
7 (20)
U9280M-H
SCL SDA Stand Start by condition Data valid Data Data/ change acknowledge valid Stop Stand- condition by
13884
Figure 7. Serial protocol
Control Byte Format
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAA AA AA AA A AAA A A A AA AA AA AA AAA A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AA AA A A AAA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAA AAAAAAAA A AAA AA AA A A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAA A A AA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AA A A
EEPROM address Mode control bits
C1 C0
Read/NWrite
R/NW
Start
A4
A3AAAA A2
A1
A0
Ackn
The control byte follows the start condition and consists of the 5-bit row address, 2 mode control bits and the read/not write-bit.
Data Transfer Sequence
Start
Control byte
Ackn
Data byte
Ackn
Data byte
Ackn
Stop
D Before the START condition and after the STOP condition the device is in standby mode and the SDAline is switched as input with pull-up resistor. D The START condition follows a control byte that determines the following operation. Bit 0 of the control byte is used to control the following transfer direction. A "0" defines a write access and a "1" a read access.
Two special control bytes enable the complete initialization of EEPROM with "0" or with "1.
1.10.2
Write Operations
1.10 EEPROM
The EEPROM has a size of 512 bits and is organized as a 32 x 16-bit matrix. To read and write data to and from the EEPROM the serial interface must be used. The interface supports one and two byte write accesses and one to n-byte read accesses to the EEPROM.
The EEPROM permits 8-bit and 16-bit write operations. A write access starts with the START condition followed by a write control byte and one or two data bytes from the master. It is completed via the STOP condition from the master after the acknowledge cycle. If the EEPROM receives the control byte, it loads the content of the addressed memory cell into a 16-bit read/write buffer. After the first data byte has been received the EEPROM starts the internal programming cycle. It consists of an erase cycle (write "zeros") and the write cycle (write "ones"). Each cycle takes about 10 ms. The write cycle is started after the stop condition and the complete buffer is stored back automatically to the EEPROM. That means for two-byte write operations, the second byte must be transferred within the erase cycle otherwise only the first byte will be stored in the EEPROM and the second byte will be ignored. Acknowledge Polling If the EEPROM is busy with an internal write cycle, all inputs are disabled and the EEPROM will not acknowledge until the write cycle is finished. This can be used to detect the end of the write cycle. The master must perform acknowledge polling by sending a start condition followed by the control byte. If the device is still busy with the write cycle, it will not return an acknowledge and the master has to generate a stop condition or perform further acknowledge polling sequences. If the cycle is complete, it returns an acknowledge and the master can proceed with the next read or write cycle.
1.10.1
EEPROM - Operating Modes
The operating modes of the EEPROM are defined via the control byte. The control byte contains the row address, the mode control bits and the read/not-write bit that is used to control the direction of the following transfer. A "0" defines a write access and a "1" a read access. The five address bits select one of the 32 rows of the EEPROM memory to be accessed. For all accesses the complete 16-bit word of the selected row is loaded into a buffer. The buffer must be read or overwritten via the serial interface. The two mode control bits C1 and C2 define in which order the accesses to the buffer are performed: High byte - low byte or low byte - high byte. The EEPROM also supports autoincrement and autodecrement read operations. After sending the start address with the corresponding mode, consecutive memory cells can be read row by row without transmission of the row addresses.
8 (20)
Rev.A1, 09-Nov-99
Preliminary Information
AAA AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAA AAAA AAA AA A A A AA AAAA A AAAA AA AA A A AA AA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAA AAA AA A A AAA AAA AA A A A AA
Read One Data Byte Read Two Data Bytes The EEPROM allows byte-, word- and current address read operations. The read operations are initiated in the same way as write operations. Every read access is initiated by sending the START condition followed by the control byte which contains the address and the read mode. After the device receives a read command it returns an acknowledge, loads the addressed word into the read\write buffer and sends the selected data byte to the master. The master has to acknowledge the received byte
Start Start Control byte Control byte A A Data byte 1 Data byte 1 A N Stop Data byte 2 N Stop
AAAA A A A AAAA A A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAA A A A A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA A A A A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AA A A A A A A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA A A A A A A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A AAAAAA A AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A A A A A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAA A AAAAAAAA A
HB: high byte; LB: low byte; R: row address Write Control Bytes A -> acknowledge Byte order Write high byte first Byte order Write low byte first
Start Control byte A Stop A4 A4 HB(R) LB(R) MSB MSB A3 A3 Row address Row address A2 A2 HB(R) LB(R) A1 A1 A0 A0 C1 C1 1 0 C0 C0 0 1 R/NW R/NW LSB LSB 0 0
AAAA AA A A A AAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAA AAA A A AAA A AA AA AAA AAA AAAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AA AA AAAAAAAAAAA AAA AA A A AA AA AA AA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAA AAA AA A A AAAAAAAAAAAAAAAAAAAA AAAA AAA AAA AA A A AA A AA A A AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAA AAA AA A A AAA AAA AA A A A AA
Write One Data Byte Write Control Byte Only Write Two Data Bytes
Start Start Control byte Control byte A A Data byte 1 Data byte 1 A A Stop Data byte 2 A Stop
Rev.A1, 09-Nov-99
1.10.3
Read Operations
Preliminary Information
if it wants to proceed the read operation. If two bytes are read out from the buffer the device increments respectively decrements the word address automatically and loads the buffer with the next word. The read mode bits determines if the low or high byte is read first from the buffer and if the word address is incremented or decremented for the next read access. If the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The master can terminate the read operation after every byte by not responding with an acknowledge (N) and by issuing a stop condition.
U9280M-H
9 (20)
A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA
Table 2. Special modes
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AAA AA A A A AA A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA A A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AA A AAAAAAAAAAAAAAAAA AAAAAAAAAA A A A A AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAA A A A AA AA A A A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A A AA A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAA A A A AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAA A A A AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AA A A AAA A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAAA A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AA A AAAA A A A A A A AA A AA A AA A AA A A AAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AAA AAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA AAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAA AA AAA AAA AA A AA A A A AA AA A A A AA
Read n Data Bytes Read Control Bytes
The EEPROM with the serial interface has its own reset circuitry. In systems with microcontrollers that have their own reset circuitry for power on reset, watchdog reset or brown-out reset, it may be necessary to bring the U505M into a known state independent of its internal reset. This is performed by reading one byte without acknowledging and then generating a stop condition.
1.10.4
U9280M-H
10 (20)
xxxxx110b
Control Byte 1100x111b 1101x111b 11xx0111b 11xx1111b
HB: high byte; LB: low byte, R: row address
Byte order
Read high byte first, addr. decrement
Byte order
Read low byte first, address increment
A -> acknowledge, N -> no acknowledge
Start
Initialization after a Reset Condition
Control byte
Description Biphase modulation Manchester modulation (not yet available !!!!) Switch power managment off -> disables switching from battery to field supply Switch power managment on -> enables automatically switching between battery and field supply Reserved
A
HB(R)
LB(R)
Data byte 1
Preliminary Information
HB(R) LB(R) A4 A4 MSB MSB A A3 A3 Row address Row address HB(R-1) LB(R+1) Data byte 2 A2 A2
With special control bytes the serial interface can be used to control the modulator stage or the power management. The EEPROM access and the serial interface are disabled in these modes until the next STOP condition. If no START or STOP condition is generated the SCL and SDA line can be used for the modulator stage. SCL is used for the modulator clock and SDA is used for the data. In that mode the same conditions for clock and data changing as normal are valid. The SCL and SDA line can be used for continuous bit transfers, an acknowledge cycle after 8 bits must not be generated.
1.10.5
A1
A1
HB(R+1)
LB(R-1)
A
Special Modes
A0
A0
----
C1
C1
1
0
---
---
Data byte n
C0
C0
0
1
HB(R-n)
LB(R+n)
Rev.A1, 09-Nov-99
R/NW R/NW LSB LSB 1 1 N HB(R+n) LB(R-n) Stop
U9280M-H
Data Transfer Sequence for Biphase and Manchester Modulation:
AAA A A A AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAA A A A A A A A A A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA A A A A A A A A A AA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA AA AA A
Start Control byte Ackn Bit 1 Bit 2AAAA.............................. Bit 3 Bit n StopAAA
Note:
After a reset of the microcontroller it is not known whether the transponder interface has been a reset too. It could be still in a receive or transmit cycle. To place the serial interface of the device into a known state, the miocrocontroller should read one byte from the device without acknowledge and generate a stop condition.
1.11 Power-on Reset
The analog front end starts working with the applied field. The EEPROM with the serial interface has its own reset circuitry. (The reset level of the front end is below the reset level of the M44C092) The microcontroller has a power-on reset circuitry with a brown-out detection. One of two reset voltage levels [1.8 V / 2.0 V] can be selected via the software (see M44C092 data sheet). If a fast instruction cycle ( < 2 s) is used the higher reset level should be selected. After a watchdog or brown-out detection reset, the serial interface and the EEPROM should be reset by reading one byte from the transponder interface device without acknowledging and generation of a STOP condition. That places the serial interface and EEPROM into a known state.
Rev.A1, 09-Nov-99
11 (20)
Preliminary Information
U9280M-H
2
2.1
Electrical Characteristics
Common Features U9280M-H
-40C to +85C 2.0 V to 6.5 V 600 mA @ 6.5 V in operating mode ( with 2 s instruction cycle) 200 A @ 2.0 V in operating mode (with 2 s instruction cycle) 1 mA @ 2.0 V in stop mode Contactless (coil 125 kHz) and battery supply
D Operating temperature range: D Operating voltage range (VBatt): D Low power consumption:
D Power supply :
2.2
Absolute Maximum Ratings
Parameters Symbol VBatt, VDD Value 0 to +7.0 with reverse protection 15 15 VSS-0.6tVINtVDD+0.6 +/- 15 +/-2
+/-1
Voltages are given relative to VSS .
AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAA AAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A
Supply voltage Max. current out of VSS-pin Max. current into VBatt-pin Input voltage (on any pin) Input/output clamp current (VSS > Vi/Vo > VDD) Min. ESD protection (100 pF through 1.5 kW) Min. ESD protection Coil 1 and Coil 2 inputs (100 pF through 1.5 kW) Operating temperature range Storage temperature range Soldering temperature (t v 10 sec) VIN IIK / IOK mA mA V mA kV kV C C C Tamb Tstg Tsd - 40 to + 85 - 40 to + 125 260
Unit V
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any condition above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating condition for an extended period may affect device reliability. All inputs
and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. VDD).
2.3
Thermal Resistance
Parameters SSO20 Symbol RthJA Value 140 Unit K/W
Junction ambient
12 (20)
Rev.A1, 09-Nov-99
Preliminary Information
AAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAA A AAAAAAA A AAAAAAAAAAAA AAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
VSS = 0 V, Tamb = -40 to 85C unless otherwise specified.
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAA A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAA A
VSS = 0 V, Tamb = -40 to 85C unless otherwise specified.
Rev.A1, 09-Nov-99
2.5
2.4
Parameters Test Conditions / Pins Brown-out protection reset threshold voltage Reset threshold voltage BOT = 1 Reset threshold voltage BOT = 0 Reset hysteresis Voltage monitor threshold voltage VM high threshold voltage VDD > VM, VMS = 1 VM high threshold voltage VDD < VM, VMS = 0 VM middle thresh. voltage VDD > VM, VMS = 1 VM middle thresh. voltage VDD < VM, VMS = 0 VM low threshold voltage VDD > VM, VMS = 1 VM low threshold voltage VDD < VM, VMS = 0 External input voltage VMI rising edge threshold VMS = 1, VDD = 3 V VMI falling edge threshold VMS = 0, VDD = 3 V
32-kHz quartz-osc. inactive 4-MHz quartz-osc. inactive) Reset current
Power down current (CPU sleep, RC oscillator active, 4-MHz quartz-osc. active) Sleep current (CPU sleep,
Parameters Power supply Operating voltage at VBatt Operating voltage at VDD Active current CPU active
Common DC Characteristics
DC Characteristics - Microcontroller M44C092
fSYSCL = 1 MHz VDD = 2.0 V VDD = 3.0 V VDD = 6.5 V fSYSCL = 1 MHz VDD = 2.0 V VDD = 3.0 V VDD = 6.5 V VDD = 6.5 V
VDD < VPOR
Test Conditions / Pins
Preliminary Information
Symbol Symbol VMThh VMThh VMThm VMThm VMThl VMThl VVMI VVMI VPOR VPOR VPOR ISleep
IReset VBatt VDD
IDD
IPD
2.0 VPOR
Min.
Min.
155 1.85
1.2
2.0
2.4
2.8
Typ.
Typ.
150
40 100 250 1.0
200 300 600
1.3 1.3
3.0 3.0 2.6 2.6 2.2 2.2
1.7 2.0 50
U9280M-H
Max.
Max.
3.25
1.85 2.2
400 2.0
800
250
1.4
2.4
2.8
6.5 6.5
70
13 (20) Unit Unit V V mV
A
A A A A
A A A
V V V V V V V V
V V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAA AAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAA A A A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
Supply voltage VDD = 1.8 to 6.5 V, VSS = 0 V, Tamb = -40 to 85C unless otherwise specified. VSS = 0 V Operation Cycle Time
AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAA A A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA AAA A AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAA A A A A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAA A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Note: The Pin BP20/NTE has a strong pull-up resistor during the reset-phase of the microcontroller
2.6
U9280M-H
14 (20) Parameters Test Conditions / Pins Timer 2 input timing Pin T2I Timer 2 input clock Timer 2 input LOW time Timer 2 input HIGH time Timer 3 input timing Pin T3I Timer 3 input clock Timer 3 input LOW time Timer 3 input HIGH time Parameters System clock cycle Output HIGH current Input LOW current (strong pull-up) Input LOW current (strong pull-down) Input leakage current Input leakage current Output LOW current Input HIGH current (pull-down) Parameters All Bidirectional Ports Input voltage LOW Input voltage HIGH Input LOW current (pull-up)
AC Characteristics
Test Conditions / Pins VDD = 1.8 to 6.5 V Tamb = -40 to 85C VDD = 2.4 to 6.5 V Tamb = -40 to 85C
VDD = 1.8 to 6.5 V VDD = 1.8 to 6.5 V VDD = 2.0 V, VDD = 3.0 V, VIL= VSS VDD = 6.5 V VDD = 2.0 V, VDD = 3.0 V, VIH = VDD VDD = 6.5 V VDD = 2.0 V, VIL= VSS VDD = 6.5 V VDD = 2.0 V, VIH= VDD VDD = 6.5 V VIL= VSS VIH= VDD VOL = 0.2 VDD VDD = 2.0 V VDD = 3.0 V, VDD = 6.5 V VOH = 0.8 VDD VDD = 2.0 V VDD = 3.0 V, VDD = 6.5 V
Test Conditions / Pins
Preliminary Information
Symbol Symbol tSYSCL Symbol tSYSCL fT3I tT3IL tT3IH fT2I tT2IL tT2IH VIL VIH IIL IOH IOL IIL IIH IIH IIH IIL
2 tSYSCL 2 tSYSCL
0.8* VDD
50 -20 -300 20 300
Min.
-0.6
-2.0
Min.
Min. 500
VSS
-50 2.0
0.6
100 100
250
-8
8
-4.0 -20 -100 4.0 20 100 -50 -600 50 600
Typ.
-1.2 -5 -16
Typ.
Typ.
1.2 5 15
0.2*VDD VDD -12
SYSCL/2
200 -100 -1200 100 1200 100 100
Rev.A1, 09-Nov-99 Max. -200 12 -2.5 Max. Max. 2000 2000 -24 2.5 22
5
Unit
MHz ns ns
mA mA mA
mA mA mA
V V A A A A A A A A A A nA nA
Unit
Unit ns
ns ns ns
AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAA A A A A AAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA AAAA A A AAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AA A AAAA A A A A A AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Parameters Test Conditions / Pins Interrupt request input timing Int. request LOW time Int. request HIGH time External system clock EXSCL at OSC1 ECM = EN Rise / fall time < 10 ns EXSCL at OSC1 ECM = DI Rise / fall time < 10 ns Input HIGH time Rise / fall time < 10 ns Reset timing Power-on reset time VDD u VPOR RC oscillator 1 Frequency Stability VDD = 2.0 to 6.5 V Temperature coefficient RC oscillator 2 - external resistor Frequency Rext = 170 kW Rext = 720 kW Stability VDD = 2.0 to 6.5 V Stabilization time 4-MHz crystal oscillator (operating range 2.2 V to 6.5 V) Frequency Start-up time Stability Integrated input / output CIN / COUT programmable capacitances in steps of 2 pF (mask programmable) 32-kHz crystal oscillator (operating range 2.0 V to 6.5 V) Frequency Start-up time Stability Integrated input / output CIN / COUT programmable capacitances in steps of 2 pF (mask programmable) External 32-kHz crystal parameters Crystal frequency Serial resistance Static capacitance Dynamic capacitance Symbol fRcOut1 f/f f/f/C fRcOut2 fRcOut2 f/f tS fEXSCL fEXSCL COUT COUT tPOR tIRL tIRH fX tSQ f/f CIN fX tSQ f/f CIN fX RS C0 C1 tIH Min. 0.02 -10 0 -10 0 100 100 0.1 0.5 0 0 32.768 30 1.5 3 32.768 0.5 Typ. 0.15
Rev.A1, 09-Nov-99 3.8 1.5 4 5 4 1 "15 10 "50 Max. 50 20 10 20 20 10 20 5 4 4
Preliminary Information
U9280M-H
15 (20) MHz ms ppm pF MHz MHz % % MHz MHz kHz s ppm pF Unit kHz kW pF fF ms pF pF % s s ns ns
A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAA A A A AAA A A A A AAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A AAAA A AAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAA A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAA AA AA A AAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Supply voltage VDD = 1.8 to 6.3 V, VSS = 0V, Tamb = -40 to 85C unless otherwise specified Parameters Test Conditions / Pins Symbol Min. Typ. Max. Power supply Operating voltage at VBatt VBatt 2.0 6.5 VBatt- VSD Operating voltage at VDD VDDB during battery supply VDD-limiter voltage during VDDC 2.4 2.9 3.2 coil supply Power management Field on detection voltage VDD > 1.8 V VFDon 2.2 2.5 2.9 Field off detection voltage VDD > 1.8 V VFDoff 0.8 Voltage drop at power-sup- IS = 1 mA, VBatt = 2 V VSD 300 ply switch Coil input Coil 1, Coil 2 Coil input current ICI 20 Coil voltage stroke during VCU > 5 V VCMS 1.8 4.0 modulation Input capacitance CIN 30 MOD pin Input LOW Voltage VIL VSS 0.2 VDD Input HIGH Voltage VIH 0.8 VDD VDD Input leakage current IIleak 10 NGAP/ FC pin Output LOW current VDD = 2,0 V IOL 0.08 0.2 0.3 VOL = 0.2*VDD Output HIGH current VDD = 2.0 V IOH -0.06 -0.15 -0.25 VOH = 0.8*VDD EEPROM Operating current during VDD = 2 V IWR 450 erase/write cycle
AAAA A A AAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAA A A AAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
U9280M-H
Parameters Test Conditions / Pins External 4 MHz crystal parameters Crystal frequency Serial resistance Static capacitance Dynamic capacitance
Equivalent circuit
2.7
16 (20)
DC Characteristics - Transponder Interface U3280M
OSCIN SCLIN
OSCOUT SCLOUT
Preliminary Information
Figure 8. Crystal equivalent circuit
Symbol
fX RS C0 C1
L
C1
C0
Min.
RS
Typ.
4.0 40 1.4 3
Rev.A1, 09-Nov-99 Max. 150 3 Unit
mA mA mA V V V mV A V V nA pF V V V
MHz W pF fF Unit
A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A AAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAA AAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AAAAAAA AAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA
Supply voltage VDD = 1.8 to 6.5 V, VSS = 0V, Tamb = 25C unless otherwise specified
Power-up to write operation Power-up to read operation Data retention time Data erase time Data erase/write cycle time Endurance Field to battery switch delay EEPROM Battery to field switch delay Delay field on to gap = 1 Power management Delay field off to gap = 0 Coil frequency Gap detection
A A A A AA A A AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAA A A A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A AAAA A A A A A A A AA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAA A A A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Supply voltage VDD = 1.8 to 6.5 V, VSS = 0V, Tamb = -40 to 85C unless otherwise specified
Rev.A1, 09-Nov-99
2.8
Parameters Coil inputs
Parameters Test Conditions / Pins Serial interface timing (internal) SCL clock frequency (int.) Serial timing (if SCL and SDA available extern) SCL clock frequency (ext.) Clock low time Clock high time SDA and SCL rise time SDA and SCL fall time Start condition setup time Start condition hold time Data input setup time Data input hold time Stop condition setup time Bus free time Input filter time Data output hold time
AC Characteristics - Transponder Interface U3280M
Tamb = 25C
for 16 bits access
Erase/write-cycles
VCoilField > 3 VDC
VCoilGap < 0.7 VDC
Test Conditions / Pins
Preliminary Information
Symbol Symbol
fSCL tLOW tHIGH tR tF tSUSTA tHDSTA tSUDAT tHDDAT tSUSTO tBUF tI tDH tFGAP1 tFGAP0 fCOIL tDEW tPUW tPUR tFBS tBFS tDR tDE ED fSC 500,000
Min.
Min.
160
300
4.7 4.0 250 0 4.7 4.7
0 4.7 4.0
10
10
2
1
1,000,000
Typ.
Typ.
125
10
9
U9280M-H
1/2
Max.
Max.
100 1000
1000 300
650
100
500
0.2
0.2
12
60
10
50
tDEW
E/Wcycles
years
Unit
Unit
kHz
kHz s s ns ns s s ns ns s s ns ns
kHz
ms
ms
ms
ms
ms
s
s
s
17 (20)
U9280M-H
3 Package Information
5.7 5.3 6.75 6.50 4.5 4.3
Package SSO20
Dimensions in mm
1.30 0.25 0.65 5.85 20 11 0.15 0.05 0.15 6.6 6.3
technical drawings according to DIN specifications 13007
1
10
4
4.1
Ordering Information
Order Number
Extended Type Number U9280M-H-xxxz-FSG3 Package SSO20 Remarks > 200 kpcs p.a. taped and reeled
Remarks: Customer ROM mask (10,000 US$) - to be defined by the customer - lead time: 18 weeks after ROM mask programming and order received
Flash Version As flash version of the U9280M-H the MARC4 M48C892 is used (available from stock).
Please select the option setting from the list below and insert ROM CRC. 18 (20) Rev.A1, 09-Nov-99
Preliminary Information
U9280M-H
Port 1
BP10 J CMOS J Pull-up - Open drain [N] - Pull-down - Open drain [P] - Pull-up strong - Pull-down strong BP13 J CMOS J Pull-up - Open drain [N] - Pull-down - Open drain [P] - Pull-up strong - Pull-down strong Open drain [P] CMOS Open drain [N] Open drain [P] Pull-up strong Pull-down strong Pull-up Pull-down Pull-up strong Pull-down strong
Port 5
BP50 -
Port 2
BP20 -
CMOS Open drain [N] Open drain [P] -
Pull-up Pull-down Pull-up strong
BP51 J CMOS J Pull-up - Open drain [N] - Pull-down - Open drain [P] - Pull-up strong - Pull-down strong BP52 J CMOS J Pull-up - Open drain [N] - Pull-down - Open drain [P] - Pull-up strong - Pull-down strong BP53 CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] Pull-up Pull-down Pull-up strong Pull-down strong Pull-up Pull-down Pull-up strong Pull-down strong Pull-up Pull-down Pull-up strong Pull-down strong
BP21 J CMOS J Pull-up - Open drain [N] - Pull-down - Open drain [P] - Pull-up strong - Pull-down strong BP22 J CMOS J Pull-up - Open drain [N] - Pull-down - Open drain [P] - Pull-up strong - Pull-down strong BP23 CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Pull-up Pull-down Pull-up strong Pull-down strong Pull-up Pull-down Pull-up strong Pull-down strong Pull-up Pull-down Pull-up strong Pull-down strong Pull-up Pull-down Pull-up strong Pull-down strong Pull-up Pull-down
Port 6
BP60 BP63 -
Port 4
BP40 BP41 BP42 BP43 -
OSC1
No integrated capacitance Internal capacitance ( ___ pF)
OSC2
No integrated capacitance Internal capacitance ( ___ pF)
ECM (Ext. clock monitor)
Enable Disable
File:____________. HEX Approval Date: ____-____-____
CRC: _____________ HEX Signature: _______________
Rev.A1, 09-Nov-99
19 (20)
Preliminary Information
U9280M-H
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic-semi.com
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
20 (20)
Rev.A1, 09-Nov-99
Preliminary Information

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